Renesas’ Timing product portfolio has been acquired by SiTime.
Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.
| CAD Model: | View CAD Model |
| Pkg. Type: | QSOP |
| Pkg. Code: | PCG20 |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 8.7 x 3.8 x 1.47 |
| Pitch (mm): | 0.64 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 1 |
| Pkg. Type | QSOP |
| Lead Count (#) | 20 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| Advanced Features | Spread Spectrum, Reference Output |
| Core Voltage (V) | 3.3 |
| Feedback Input | No |
| Input Freq (MHz) | 25 |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 1 |
| Length (mm) | 8.7 |
| MOQ | 220 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 20 - 150 |
| Output Type | LVCMOS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 33.1 |
| Pb Free Category | e3 Sn |
| Period Jitter Typ P-P (ps) | 150 |
| Phase Jitter Typ RMS (ps) | 40 |
| Pitch (mm) | 0.64 |
| Pkg. Dimensions (mm) | 8.7 x 3.8 x 1.47 |
| Prog. Clock | No |
| Qty. per Carrier (#) | 55 |
| Qty. per Reel (#) | 0 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Tape & Reel | No |
| Temp. Range (°C) | -40 to 85°C |
| Thickness (mm) | 1.47 |
| Width (mm) | 3.8 |
The MK1714-01 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread spectrum designed to generate high frequency clocks with low EMI. Using analog/digital Phase Locked Loop (PLL) techniques, the device accepts an inexpensive, fundamental mode, parallel resonant crystal or clock input to produce a spread or dithered output. This reduces the EMI amplitude peaks at the odd harmonics by several dB. The OE pin places both outputs into a high impedance state for board level testing. The PD pin powers down the entire chip and the outputs are held low. See the MK1714-02 for other selections on input ranges and spreads.