Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | WAFER |
| Pkg. Code: | DICEW |
| Lead Count (#): | |
| Pkg. Dimensions (mm): | 0.0 x 0.0 x 0.0 |
| Pitch (mm): |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | |
| Pb (Lead) Free | Yes |
| ECCN (US) | |
| HTS (US) |
Product Attributes
| Lead Count (#) | 0 |
| Carrier Type | WFP |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | 0 to 85°C |
| Country of Wafer Fabrication | UNITED STATES |
| Application | CXP, 100G Ethernet SR10, 164G FDR InfiniBand |
| Channels (#) | 12 |
| Data Rate Max (Gbps) | 16 |
| Function | Linear TIA |
| MOQ | 112 |
| Pkg. Dimensions (mm) | 0.0 x 0.0 x 0.0 |
| Pkg. Type | WAFER |
| Price (USD) | $67.84518 |
| Published | No |
| Qty. per Carrier (#) | 0 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
Resources for HXR6112
Description
The HXR6112 Transimpedance Limiting Amplifier array is a member of IDT’s family of Optical Receiver Transmitter Array (ORTA) products targeted at the parallel optical links market. Together with a PIN detector array or discrete detectors, high-capacity, high-availability optical links can be designed for datacom applications. The 3.3V SiGe device integrates the transimpedance pre-amplifier, the limiting post-amplifier and a versatile CML output stage for twelve optical channels.