Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | PLCC |
| Pkg. Code: | NGH |
| Lead Count (#): | 44 |
| Pkg. Dimensions (mm): | 16.51 x 16.51 x 0.00 |
| Pitch (mm): | 1.27 |
Environmental & Export Classifications
| RoHS (IS82C50A-5Z) | Download |
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | |
| HTS (US) |
Product Attributes
| Carrier Type | Tube |
| MOQ | 104 |
| Lead Count (#) | 44 |
| Length (mm) | 16.5 |
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| Pb Free Category | Pb-Free 100% Matte Tin Plate w/Anneal-e3 |
| Pitch (mm) | 1.3 |
| Pkg. Dimensions (mm) | 16.5 x 16.5 x 0.00 |
| Pkg. Type | PLCC |
| Temp. Range (°C) | -40 to +85°C |
| Width (mm) | 16.5 |
Resources for 82C50A
Description
The 82C50A Asynchronous Communication Element (ACE) is a high performance programmable Universal Asynchronous Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single chip. Using Intersil's advanced Scaled SAJI IV CMOS Process, the ACE will support data rates from DC to 625K baud (0-10MHz clock). The ACE's receiver circuitry converts start, data, stop, and parity bits into a parallel data word. The transmitter circuitry converts a parallel data word into serial form and appends the start, parity, and stop bits. The word length is programmable to 5, 6, 7, or 8 data bits. Stop bit selection provides a choice of 1, 1. 5, or 2 stop bits. The Baud Rate Generator divides the clock by a divisor programmable from 1 to 216-1 to provide standard RS- 232C baud rates when using any one of three industry standard baud rate crystals (1. 8432MHz, 2. 4576MHz, or 3. 072MHz). A programmable buffered clock output (BAUDOUT) provides either a buffered oscillator or 16X (16 times the data rate) baud rate clock for general purpose system use. To meet the system requirements of a CPU interfacing to an asynchronous channel, the modem control signals RTS, CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs have been designed with full TTL/CMOS compatibility in order to facilitate mixed TTL/NMOS/CMOS system design.