Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | SOIC |
| Pkg. Code: | PSG20 |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 12.8 x 7.6 x 2.34 |
| Pitch (mm): | 1.27 |
Environmental & Export Classifications
| Pb (Lead) Free | Yes |
| Moisture Sensitivity Level (MSL) | 1 |
| ECCN (US) | |
| HTS (US) |
Product Attributes
| Lead Count (#) | 20 |
| Pb (Lead) Free | Yes |
| Carrier Type | Reel |
| Bus Width (bits) | 8 |
| Core Voltage (V) | 5 |
| Function | Latch |
| Length (mm) | 12.8 |
| MOQ | 1000 |
| Moisture Sensitivity Level (MSL) | 1 |
| Package Area (mm²) | 97.3 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 12.8 x 7.6 x 2.34 |
| Pkg. Type | SOIC |
| Price (USD) | $0.62115 |
| Published | No |
| Qty. per Carrier (#) | 0 |
| Qty. per Reel (#) | 1000 |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Speed Grade | C |
| Tape & Reel | Yes |
| Temp. Range (°C) | -40 to 85°C |
| Thickness (mm) | 2.34 |
| Width (mm) | 7.6 |
Resources for 74FCT573T
Description
The 74FCT573T is an Octal Transparent CMOS Latch built with 3-state outputs. This transparent latch is intended for bus-oriented applications. When Latch Enable (LE) is high, flip-flops appear transparent to the data; and when Latch Enable is low, the data that meets the set-up time is latched. The 74FCT573T CMOS latch operates at -40C to +85C. (For Mil version, see 54FCT573T).