The 8S89833I is a high speed 1-to-4 Differential-to-LVDS Fanout Buffer with Internal Termination. The 8S89833I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, and CML to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin which may be useful for system test and debug purposes. The 8S89833I is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications.

特長

  • Four differential LVDS outputs
  • IN, nIN input pair can accept the following differential input levels: LVPECL, LVDS, CML
  • Output frequency: 2GHz
  • Cycle-to-cycle jitter, RMS: 3.5ps (maximum)
  • Additive phase jitter, RMS: 0.03ps (typical)
  • Output skew: 30ps (maximum)
  • Part-to-part skew: 200ps (maximum)
  • Propagation Delay: 600ps (maximum)
  • Full 3.3V supply mode
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

tune製品選択

製品名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Active VFQFPN 16 I はい Tray
Availability
Active VFQFPN 16 I はい Reel
Availability

descriptionドキュメント

タイトル language 分類 形式 サイズ 日付
データシート
star 8S89833 Datasheet データシート PDF 557 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-846 Termination - LVDS アプリケーションノート PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PCN# : PCN200016 Change Shipping Media on Select Package 製品変更通知 PDF 2.97 MB
PCN# : TB1912-02(R1) Convert Shipping Media from Tube or Tray to Cut Reel 製品変更通知 PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media from Tube or Tray to Cut Reel 製品変更通知 PDF 5.61 MB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 製品変更通知 PDF 983 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 544 KB
その他資料
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB

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