Overview

Description

The 72T18115 is a 256K x 18 / 512K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.

Features

  • User selectable HSTL/LVTTL Input and/or Output
  • 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Output voltage
  • 3.3V Input tolerant
  • Program programmable flags by either serial or parallel means
  • Big-Endian/Little-Endian user selectable byte representation
  • Auto power down minimizes standby power consumption
  • Master Reset clears entire FIFO
  • Partial Reset clears data, but retains programmable settings
  • Empty, Full and Half-Full flags signal FIFO status
  • Output enable puts data outputs into high impedance state
  • JTAG port, provided for Boundary Scan function
  • Available in 240-pin PBGA package
  • Easily expandable in depth and width
  • Independent Read and Write Clocks (permit reading and writing simultaneously)
  • Industrial temperature range (–40C to +85C) is available

Documentation

Document title Document type
Type
Date Date
PDF 384 KB Datasheet
TXT 14 KB Application Note
PDF 123 KB Guide
PDF 524 KB Product Change Notice
PDF 24 KB Product Change Notice
PDF 99 KB Product Change Notice
PDF 729 KB Product Change Notice
PDF 80 KB Product Change Notice
PDF 38 KB Product Change Notice
PDF 211 KB Product Change Notice
PDF 26 KB Product Change Notice
PDF 23 KB Product Change Notice
PDF 274 KB Product Change Notice
13 items

Design & Development

Models

Models

Title Type Type Date Date
ZIP 2 KB Model - BSDL
ZIP 30 KB Model - IBIS
2 items

Support