The Renesas PCIe® Gen3 retimer family offers the industry a blend of top analog performance, lower power and the most system-level features in signal retimers optimized for demanding 2.5Gbps, 5Gbps and 8Gbps applications in computing, storage and communications.
Features of the Renesas PCI retimers include:
The Renesas PCIe retimers (signal conditioners) are used to improve signal integrity for enhancing system performance and reliability across long PCB traces or cables. The PCIe retimers remove both random and deterministic jitter from the input signal eliminating inter-symbol interference (ISI), and reset the output jitter budget. The devices provide 8, 16 or 32 differential, 8GT/s PCI Express 3.0 channels, supporting 4, 8, or 16 lanes, respectively. The PCIe retimers also fully support PCI Express 5GT/s and 2.5GT/s features.
The Renesas PCIe retimers feature a full CDR architecture with adaptive Decision Feedback Equalizer (DFE) and extensive control options accessed via serial interface. The devices feature a per-channel mini controller that enables self-configuration for optimum performance using automatic adjustment via equalization training. The mini controller manages the functions of each link including 128/130b coding, down-shift for compatibility with PCIe Gen1 and Gen2, receiver detection and termination control.
All of the Renesas PCIe retimers implement a non-linear, adaptive, multi-stage equalizer, with analog front-end and 5-tap DFE. The feedback filter of the DFE allows ISI distortion from previous symbols to be removed completely, and with digital quantization eliminates filter output noise. Filter tap weights can be adjusted via serial configuration.
Default equalization, de-emphasis, and TX full-scale swing settings are pin-programmable. The PCIe retimers support extensive configurability for every operating feature configuration as an SMBus or I2C slave device. Additionally, they provide a master mode of operation to download configuration data from a serial-EEPROM. The serial bus also allows for inspection of the numerous status registers.
The PCIe retimers provide a default signal termination setting of 100 ohms nominal for calibrated input terminations and can be programmed to 85 ohms nominal if desired. The input signal detection thresholds can be adjusted for the valid active signal level, supporting electrical idling.
In addition, the PCIe retimers support both JTAG and AC JTAG to facilitate production board testing, and a built-in pattern generator is provided to enable convenient lab and field tests. Extensive software is available to support test and debug, including a PC utility for setting and saving device configuration, and an eye capture tool supporting remote in-field diagnosis.
The retimer devices use supply voltages of 1.0V, 1.8V, and 3.3V. Multiple features are provided to minimize power consumption, including Active State Power Management (ASPM) of each link.
High-speed signals can deteriorate to unacceptable levels by the time they reach end receivers, due to transmitter, receiver, and channel characteristics. PCIe retimers ensure minimized jitter and maximized eye opening at the target receiver by compensating for cable and PCB trace attenuation and ISI jitter. This is accomplished by boosting the transmitted signal, by equalizing the received signal, or by doing both when either option by itself is not sufficient due to channel length or due to discontinuities generated by vias and connectors. Renesas retimers are ideal for solving signal integrity problems in blade servers, enterprise storage, communication systems, and cloud computing.
IDT PCI Express 3.0 retimer for high-speed signal conditioning up to 8Gbps. Delivers signal quality over extended distances while offering simplified design by alleviating board layout constraints. These devices incorporate advanced receive equalization and transmit de-emphasis capabilities, as well as diagnostic features that help IDT customers achieve a simplified design with faster time-to-market. The devices all offer power savings modes for the lowest-possible power consumption. Presented by Ken Curt, Product Manager, Integrated Device Technology, Inc. Learn more at www.idt.com/go/PCIeSIP.