This is the evaluation kit for the 8A34003, 8A34004, 8A34013, and 8A34043. The 8A34003 is functionally a superset of these products, making it suitable to evaluate any of the four. Please return to the device product page for more information on each specific device. The 8A34003 provides four independent timing channels that can be configured as Digital PLLs (DPLLs) or as Digitally Controlled Oscillators (DCOs). The DPLL channels can be used for jitter attenuation and frequency translation. The DCOs can be programmed to synthesize the desired frequency and they can be steered by external software with resolution of 1.11E-16. The DPLLs can lock to virtually any frequency from 1kHz to 1GHz and the DPLLs and DCOs can generate virtually any frequency from 0.5Hz to 1GHz with typical jitter below 150fs RMS from 12kHz to 20MHz.
|Manual - Hardware
|PDF 1.99 MB
PWM Co-located Carrier, PWM Squelch, and PWM Reference Switching Description for ClockMatrix DevicesLog in to Download PDF 96 KB
|PDF 199 KB