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551S

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Low Skew 1 to 4 Clock Buffer

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Overview

The 551S is a low cost, high-speed single input to four output LVCMOS clock buffer that offers a best-in-class additive phase jitter of sub 50fs.

551S Block Diagram
551S Pinout - DFN
551S Pinout - SOIC
551S Block Diagram
551S Pinout - DFN
551S Pinout - SOIC
  • Low additive phase jitter RMS: 50fs
  • Extremely low skew outputs (50ps)
  • Low-cost clock buffer
  • Packaged in an 8-pin SOIC and 8-pin DFN, Pb-free
  • Input/Output clock frequency up to 200MHz
  • Non-inverting output clock
  • Ideal for networking clocks
  • Operating voltages: 1.8V to 3.3V
  • Output Enable mode tri-state outputs
  • Advanced, low-power CMOS process
  • Extended temperature range: -40 °C to +105 °C

Documentation

Featured Documentation
Type Title Date
Datasheet
551S Datasheet
PDF 274 KB
Application Note
Termination Options for High-Speed LVCMOS Driver Clock Drivers
PDF 187 KB
Overview
Clock Distribution Overview
PDF 217 KB
Product Change Notice
PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets
PDF 268 KB
Product Change Notice
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly
PDF 611 KB
Product Change Notice
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly
PDF 611 KB
Application Note
AN-842 Thermal Considerations in Package Design and Selection
PDF 495 KB
Application Note
AN-840 Jitter Specifications for Timing Signals
PDF 442 KB
Application Note
AN-815 Understanding Jitter Units
PDF 565 KB
9 items

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

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Diagram of ECAD Models

Models
Type Title Date
Model - IBIS
551S IBIS Model
ZIP 27 KB
1 item

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Support Communities

  1. What is the difference between theses 1 to 4 LVCMOS buffers?

    What is the difference between the following 1 to 4 LVCMOS buffers: 553S, 551S, 651S, 621S & 524S, 74FCT38074S and 5PB1104?

    Apr 23, 2024
  2. Sparkfun DA16200: "Failed to initialize RAMCode" when flashing using J-Link

    ... FBOOT.bin, 0x10000000 Downloading file [FBOOT.bin]... J-Link: Flash download: Bank 0 @ 0x10000000: 1 range affected (32768 bytes) J-Link: Flash download: Total: 4.551s (Prepare: 1.573s, Compare: 0.866s, Erase: 0.398s, Program: 0.703s, Verify: 0.391s, Restore: 0.616s) J-Link: Flash download: Program speed ...

    Feb 8, 2023
  3. Sparkfun DA16200: "Failed to initialize RAMCode" when flashing using J-Link

    ... FBOOT.bin, 0x10000000 Downloading file [FBOOT.bin]... J-Link: Flash download: Bank 0 @ 0x10000000: 1 range affected (32768 bytes) J-Link: Flash download: Total: 4.551s (Prepare: 1.573s, Compare: 0.866s, Erase: 0.398s, Program: 0.703s, Verify: 0.391s, Restore: 0.616s) J-Link: Flash download: Program speed ...

    Feb 8, 2023

Videos & Training

This video overviews the LVCMOS Fanout Buffers, showcasing their best-in-class performance with extremely low phase jitter, minimal output skew, and low power consumption, along with other competitive features.

News & Blog Posts

News
Mar 24, 2015
IDT Introduces Ultra-Low-Jitter Family of LVCMOS Clock Buffers