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8SLVD1204-33I

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Product Longevity: 2040

2:4, LVDS Output Fanout Buffer, 3.3V

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Features

  • Four low skew, low additive jitter LVDS output pairs
  • Two selectable differential clock input pairs
  • Differential PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL
  • Maximum input clock frequency: 2GHz
  • LVCMOS/LVTTL interface levels for the control input select pin
  • Output skew: 20ps (maximum)
  • Propagation delay: 310ps (maximum)
  • Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz - 20MHz: 100fs (maximum)
  • Full 3.3V supply voltage
  • Lead-free (RoHS 6), 16-Lead VFQFN packaging
  • -40°C to 85°C ambient operating temperature
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8SLVD1204-33I - Block Diagram
8SLVD1204-33I - Pinout
8SLVD1204-33I - Block Diagram
8SLVD1204-33I - Pinout

Description

The IDT8SLVD1204-33I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVD1204-33I is characterized to operate from a 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVD1204-33I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

For a 2.5 V version of this device, please refer to the 8SLVD1204I.

Parameters

Attributes Value
Temp. Range (°C) -40 to 85°C

Package Options

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 3.0 x 3.0 x 1.0 16 0.5

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Overview of IDT's 8LSVP (LVPECL) and 8SLVD (LVDS) families of low-jitter fanout buffers from IDT. Fanout buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. IDT's high-performance, low additive phase noise, differential clock fan-out buffers offer up to 2 GHz clock operation, low additive phase jitter (12kHz - 20MHz) of 50 to 100 femtoseconds RMS max, fast output rise & fall times (less than 150ps), and single and dual channel functions (dual: matched propagation delay). Presented by Baljit Chandhoke, Product Marketing Manager at Integrated Device Technology, Inc. To learn more about IDT's industry-leading portfolio of fanout buffers, visit Renesas's RF Buffer page.

 

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