Features
- Four low skew, low additive jitter LVDS output pairs
- Two selectable differential clock input pairs
- Differential PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL
- Maximum input clock frequency: 2GHz
- LVCMOS/LVTTL interface levels for the control input select pin
- Output skew: 20ps (maximum)
- Propagation delay: 310ps (maximum)
- Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz - 20MHz: 100fs (maximum)
- Full 3.3V supply voltage
- Lead-free (RoHS 6), 16-Lead VFQFN packaging
- -40°C to 85°C ambient operating temperature
Description
The IDT8SLVD1204-33I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVD1204-33I is characterized to operate from a 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVD1204-33I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
For a 2.5 V version of this device, please refer to the 8SLVD1204I.
Parameters
| Attributes | Value |
|---|---|
| Outputs (#) | 4 |
| Inputs (#) | 2 |
| Channels (#) | 1 |
| Input Freq (MHz) | 0 - 2000 |
| Output Freq Range (MHz) | 0 - 2000 |
| Output Skew (ps) | 20 |
| Adjustable Phase | No |
| Noise Floor (dBc/Hz) | -160 |
| Additive Phase Jitter Typ RMS (fs) | 95 |
| Output Type | LVDS |
| Supply Voltage (V) | 3.3 - 3.3 |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 3.0 x 3.0 x 1.0 | 16 | 0.5 |