The 9ZXL0853E is a Gen1–5  compliant, enhanced performance differential clock buffer. The device supports complex clocking architectures like SRIS and SRNS. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL0853E has an SMBus Write Lock feature for increased device and system security. The device also features up to 9 selectable SMBus addresses.
 

Features

  • PCIe Gen1–5 compliance
  • SMBus Write Protect feature; increase system security
  • UPI/QPI support
  • Supports PCIe SRIS and SNRS clocking  
  • LP-HCSL outputs with 85Ω Zout; eliminate 4 resistors per output pair
  • 8 OE# pins; hardware control of each output
  • 9 selectable SMBus addresses; multiple devices can share same SMBus segment
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz and 133.33MHz ZDB mode
  • 6 × 6 mm 48-VFQFPN package; small board footprint
 

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9ZXL0853EKILF
Active VFQFPN 48 I Yes Tray
Availability
9ZXL0853EKILFT
Active VFQFPN 48 I Yes Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9ZXL06x2E-9ZXL08xxE-9ZXL12x2E Family Datasheet Datasheet PDF 495 KB
Application Notes & White Papers
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5 Application Note PDF 244 KB
AN-975 Cascading PLLs Application Note PDF 255 KB
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 235 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-808 PCI Express/HCSL Termination Application Note PDF 137 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
Downloads
9ZXL0853E IBIS Model Model - IBIS ZIP 19 KB
Other
PCI Express Timing Solutions Overview Overview PDF 275 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB

Boards & Kits

Part Number Title Type Company
EVK9ZXL1951D Evaluation Kit for 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI Renesas