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9ZXL0651E

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6-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer

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Features

  • LP-HCSL outputs with 85Ω Zout; eliminate 24 resistors, save 48mm² of area
  • PCIe Gen 1–5 compliance
  • 6 OE# pins; hardware control of each output
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz PLL Mode; UPI support
  • 5mm × 5mm 40-VFQFPN package; small board footprint
Find Other Products in Application-Specific Clocks
9ZXL04x1-06x1-08x1-12x1 - Block Diagram
9ZXL0651E - Pinout
9ZXL04x1-06x1-08x1-12x1 - Block Diagram
9ZXL0651E - Pinout

Description

The 9ZXL0651E is a second-generation, enhanced-performance DB800ZL derivative. The part is a pin-compatible upgrade to the 9ZXL0651A while offering a much-improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications.

 

Parameters

AttributesValue
Diff. Outputs6
Diff. Output SignalingLP-HCSL
Output Freq Range (MHz)1 - 400
Diff. Inputs1
Diff. Input SignalingHCSL
Accepts Spread Spec InputYes
Power Consumption Typ (mW)257
Supply Voltage (V)3.3 - 3.3
Output TypeLP-HCSL
Diff. Termination Resistors24
Package Area (mm²)81
Battery BackupNo
Battery SealNo
CPU Supervisory Function PORNo
Crystal Frequency TrimmingNo
Frequency Out PinNo
Inputs (#)1
Input Freq (MHz)33 - 150
FunctionZero Delay Buffer
Input TypeHCSL
Output Banks (#)1
Core Voltage (V)3.3
Output Voltage (V)0.7

Package Options

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
VFQFPN5.0 x 5.0 x 0.9400.4

Applications

  • Servers/High-performance Computing
  • nVME Storage
  • Networking
  • Accelerators
  • Industrial Control

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

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