The 9FGV1005 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1005 provides 2 copies of a single non-spread spectrum output frequency and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.

Features

  • PCIe Gen1–5 compliant
  • PCIe Gen5 Common Clock jitter < 80fs RMS
  • 284fs RMS typical phase jitter at 156.25MHz (12kHz–20MHz)
  • 2 programmable output pairs plus 1 LVCMOS REF outputs
  • 1 integer output frequency per configuration
  • 1MHz–325MHz output frequency (LVDS or LP-HCSL)
  • 1MHz–200MHz output frequency (LVCMOS)
  • 1.8V to 3.3V core VDD
  • Individual 1.8V to 3.3V VDDO for each programmable output pair
  • Supports HCSL, LVDS and LVCMOS I/O standards
  • Supports AC-coupled LVPECL and CML logic – see AN-891
  • 3 × 3 mm 16-LGA packages with 50MHz integrated crystal option
  • Supported by Timing Commander™ software

Product Options

This device is factory-configurable. Try the Custom Part Configuration Utility.
Orderable Part ID Part Status Output Type Output Freq Range (MHz) Supply Voltage (V) Xtal Freq (MHz) Carrier Type Buy Sample
Active LP-HCSL, LVCMOS, LVDS 1 - 325 , 1.8, 2.5, 3.3 8 - 50 Tray
Availability
Active LP-HCSL, LVCMOS, LVDS 1 - 325 , 1.8, 2.5, 3.3 8 - 50 Reel
Availability
Active LP-HCSL 50, 100, 125, 156.25 , , , 3.3 25 Tray
Availability
Active LP-HCSL 50, 100, 125, 156.25 , 3.3 25 Reel
Availability
Active LP-HCSL 50, 100, 125, 156.25 , 1.8 25 Tray
Availability
Active LP-HCSL 50, 100, 125, 156.25 , 1.8 25 Reel
Availability
Active LP-HCSL 156.25, 161.1328125, 312.5, 322.265625 , 3.3 39.0625 Tray
Availability
Active LP-HCSL 156.25, 161.1328125, 312.5, 322.265625 , 3.3 39.0625 Reel
Availability
Active LP-HCSL 156.25, 161.1328125, 312.5, 322.265625 , 1.8 39.0625 Tray
Availability
Active LP-HCSL 156.25, 161.1328125, 312.5, 322.265625 , 1.8 39.0625 Reel
Availability
Active LP-HCSL 50, 100, 125, 156.25 , 3.3 50 Tray
Availability
Active LP-HCSL 50, 100, 125, 156.25 , 3.3 50 Reel
Availability
Active LP-HCSL 50, 100, 125, 156.25 , 1.8 50 Tray
Availability
Active LP-HCSL 50, 100, 125, 156.25 , 1.8 50 Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9FGV1001C-9FGV1005C Datasheet Datasheet PDF 706 KB
9FGV1005C011 Datasheet Addendum Datasheet PDF 144 KB
9FGV1005C012 Datasheet Addendum Datasheet PDF 144 KB
9FGV1005CQ505 Datasheet Addendum Datasheet PDF 144 KB
9FGV1005CQ506 Datasheet Addendum Datasheet PDF 144 KB
9FGV1005C001 Datasheet Addendum Datasheet PDF 144 KB
9FGV1005C002 Datasheet Addendum Datasheet PDF 144 KB
User Guides & Manuals
9FGV1005 Register Descriptions and Programming Guide Manual - Software PDF 293 KB
9FGV1005 PhiClock PCIe Timing Commander Software User Guide Manual - Software PDF 1.50 MB
9FGV100x Register Descriptions and Programming Guide Manual - Software PDF 401 KB
Application Notes & White Papers
Driving Differential, Single-Ended, and/or Frequency Generator Crystal Inputs Application Note PDF 134 KB
9FGV100x: PhiClock OTP Procedure Application Note PDF 222 KB
AN-1014 Microstrip vs Stripline: Crosstalk and RMS Phase Jitter Application Note PDF 486 KB
AN-975 Cascading PLLs Application Note PDF 255 KB
AN-918 Programmable Clocks vs Crystal Oscillators Application Note PDF 307 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PCN# : PCN200009 (R1) PhiClock Family Revision Update Product Change Notice PDF 129 KB
PCN# : PCN200009 PhiClock Family Revision Update Product Change Notice PDF 143 KB
Downloads
9FGV1005C Timing Commander Personality File Software TCP 3.94 MB
9FGV1005 IBIS Model Model - IBIS ZIP 98 KB
Other
Clock Distribution Overview 日本語 Overview PDF 217 KB
I2C GUI Tool User Guide Miscellaneous PDF 507 KB
PCI Express Timing Solutions Overview Overview PDF 275 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB

Boards & Kits

Part Number Title Type Company
EVK9FGV1005 Evaluation Kit for 9FGV1005 Programmable PhiClock™ Generator
EVK9FGV1005Q5 Evaluation Kit for 9FGV1005 Programmable PhiClock™ Generator with Internal 50MHz Crystal