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6V31021

Not Recommended for New Designs

4-Output Low Power Fanout Buffer For PCIe Gen3 And 10G Ethernet

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Features

  • 4 - low power differential output pairs
  • Individual OE# control of each output pair
  • Low power differential outputs
  • Power down mode when all OE# are high
  • Industrial temperature range
  • 20-pin MLF
  • Output cycle-cycle jitter <15 ps additive
  • Output to Output skew: <50 ps
  • PCIe Gen3 additive phase jitter <0.3 ps rms
  • 10.3125G / 64 additive phase jitter <100 fs rms
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6V31021 - Block Diagram
6V31021 - Pinout
6V31021 - Block Diagram
6V31021 - Pinout

Description

The IDT6V31021 is a 4-output low- power differential buffer. Each output has its own OE# pin. It has a maximum operating frequency of 167 MHz and supports all SERDES clock frequencies for Freescale QorIQ CPUs.

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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

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