Overview

Description

The 8A34011 Line Card Synchronizer for IEEE 1588 regenerates and distributes ultra-low jitter; precision timing signals that are locked to IEEE 1588 and Synchronous Ethernet (SyncE) reference sources elsewhere in a system. The device can be used to precisely synchronize IEEE 1588 Time Stamp Units (TSUs) and SyncE ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media that introduce clock propagation delays. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device can be used to actively measure and compensate for clock propagation delays across backplanes and across circuit boards to ensure the distribution of accurate time and phase with minimal time error between IEEE 1588 TSUs in a system. The device supports multiple independent timing channels for: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 TSUs.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.

Features

  • Eight independent timing channels
  • Jitter output below 150fs RMS (typical)
  • Digital PLLs (DPLLs) lock to any frequency from 1kHz to 1GHz
  • DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • DPLLs comply with ITU-T G.8262 for Synchronous Ethernet (SyncE)
  • IEEE 1588 Support:
    • Precise (1ps) resolution for phase measurement and control
    • All outputs/inputs can be configured to decode/encode PWM clock signals
    • PWM can be used to transmit and receive embedded frame and sync pulses; as well as Time of Day (ToD) and other data
  • Supports up to 8 differential or 16 single-ended reference clock inputs
  • Supports up to 12 differential outputs or 24 LVCMOS outputs
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • Serial processor ports support 1MHz I2C or 50MHz SPI
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory 
    • Standard external I2C EPROM via separate I2C Master Port

Documentation

Type
Date
PDF 1.91 MB Datasheet
PDF 247 KB Application Note
PDF 164 KB Release Note
PDF 195 KB Schematic
PDF 465 KB Application Note
PDF 502 KB Product Change Notice
PDF 199 KB Application Note
PDF 164 KB Application Note
PDF 140 KB Application Note
PDF 215 KB Manual - Software
PDF 2.54 MB Guide
PDF 1.57 MB Application Note
PDF 84 KB Application Note
PDF 275 KB Application Note
XLSX 321 KB Other
PDF 936 KB Guide
PDF 1.16 MB Application Note
PDF 400 KB White Paper
PDF 320 KB Overview
PDF 1.92 MB Application Note
PDF 103 KB Release Note
PDF 135 KB Product Change Notice
PDF 692 KB Application Note
PDF 2.13 MB Application Note
PDF 10.53 MB Guide
PDF 113 KB Product Change Notice
PDF 2.35 MB Guide
PDF 213 KB Guide
PDF 393 KB Application Note
PDF 231 KB Application Note
PDF 552 KB Application Note
PDF 385 KB Application Note
PDF 272 KB Application Note
PDF 406 KB Application Note
PDF 304 KB Application Note
PDF 38 KB Device Errata
PDF 143 KB Guide
PDF 1.62 MB Application Note
PDF 354 KB Application Note
PDF 839 KB Application Note
PDF 2.35 MB Guide
PDF 390 KB Application Note
PDF 486 KB Manual - Hardware
PDF 880 KB Application Note
PDF 584 KB Application Note
PDF 301 KB Product Change Notice
PDF 162 KB Application Note
PDF 550 KB Application Note
PDF 739 KB Application Note
PDF 633 KB Application Note
PDF 123 KB Product Change Notice
PDF 435 KB Product Change Notice
PDF 479 KB Application Note
PDF 442 KB Application Note
PDF 566 KB Application Note
PDF 2.67 MB Manual - Hardware
PDF 976 KB Application Note
PDF 659 KB Application Note
PDF 288 KB Schematic
PDF 324 KB Application Note
60 items

Design & Development

Software & Tools

Software Downloads

Type
Date
ZIP 51.88 MB Software & Tools - Other
ZIP 18.02 MB Software & Tools - Other
ZIP 278 KB Software & Tools - Other
ZIP 73 KB Software & Tools - Other
ZIP 177 KB Software & Tools - Other
ZIP 177 KB Software & Tools - Other
6 items

Models

Models

Type Date
ZIP 2.55 MB Model - IBIS
ZIP 3 KB Model - BSDL
BSDL 15 KB Model - BSDL
PDML 2 KB Model - Thermal
PDML 3 KB Model - Thermal
5 items

Support

IDT ClockMatrix™ Timing Solution for 100Gbps Interface Speeds (IEEE 1588, OTN, and SyncE)

Introducing the IDT ClockMatrix™ family of devices - high-performance, precision timing solutions designed to simplify clock designs for applications with up to 100 Gbps interface speeds. 

They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation and phase alignment. A range of devices in the family support BBU, OTN, SyncE, synthesizer and jitter attenuator applications with several density options for each.

For more information, visit www.idt.com/clockmatrix.