Features
- Two 1:4, low skew, low additive jitter LVPECL output pairs
- Two differential clock input pairs
- Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML
- Maximum input clock frequency: 2GHz
- Output skew: 8ps (typical)
- Propagation delay: 270ps (maximum)
- Low additive phase jitter, RMS: 47fs (maximum)
- Full 3.3V and 2.5V supply voltage
- Maximum device current consumption (IEE): 88mA (maximum)
- Available in lead-free (RoHS 6), 28-Lead VFQFN package
- -40°C to 85°C ambient operating temperature
- Supports case temperature ≤105°C operations
Description
The 8SLVP2104I is a high-performance differential dual LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP2104I is characterized to operate from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP2104I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enable easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
Parameters
| Attributes | Value |
|---|---|
| Temp. Range (°C) | -40 to 85°C (Tc ≤ 105°C) |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.8 | 28 | 0.5 |