High-Speed Embedded AI-Based Image Processing Device with Dynamically Reconfigurable Processor (DRP) Technology

Overview

The RZ/A2M MPU is designed for e-AI based imaging in smart appliances, networked cameras, service robots, scanner products, and industrial machinery that require high-speed image processing. It features a unique hybrid approach to image recognition and machine vision by combining proprietary DRP technology for fast pre-processing of image data and feature extraction, closely coupled to an Arm® Cortex®-A9 CPU.

DRP Technology and Applications

Get Started Using RZ/A2M

Key Features

Item RZ/A2M
Part name/Use/Package 176-pin R7S921040VCBG
Industry usage etc.
176-pin BGA (13mm x 13mm)
0.8mm pitch
256-pin R7S921041VCBG
Industry usage etc.
256-pin BGA (11mm x 11mm)
0.5mm pitch
R7S921051VCBG
Industry usage etc.
256-pin BGA (11mm x 11mm)
0.5mm pitch
272-pin R7S921042VCBG
Industry usage etc.
272-pin BGA (17mm x 17mm)
0.8mm pitch
R7S921052VCBG
Industry usage etc.
272-pin BGA (17mm x 17mm)
0.8mm pitch
324-pin R7S921043VCBG
Industry usage etc.
324-pin BGA (19mm x 19mm)
0.8mm pitch
R7S921053VCBG
Industry usage etc.
324-pin BGA (19mm x 19mm)
0.8mm pitch
Power supply voltage 3.3V/1.8V/1.2V
Maximum operating frequency 528MHz
CPU core Arm® Cortex®-A9 (with Jazelle® and NEON)
On-chip RAM Large-capacity memory: 4MB
(For video display/work area: 128KB are shared with data retention)
Cache memory Primary cache memory: 64KB (separated 32K instruction/32K data, TLB128 entry)
Secondary cache memory: 128KB (with CoreLink™ Level 2 Cache Controller L2C-310)
External memory Bus clock: Up to 132MHz
Direct connection to SRAM, byte select SRAM, SDRAM, and burst ROM (clock synchronous/clock asynchronous) using bus state controller
Address/Data multiplexer I/O (MPX) interface supported
Address space: 64MB x 6
Data bus width: External 8/16 bits
Graphics functions Video display controller (1 channel of video input and 1 channel of panel output which supports LVDS)
Sprite engine
Capture engine unit (CMOS camera interface)
Distortion correction engine x 1 channel (requires nondisclosure agreement)
2D drawing engine
MIPI CSI-2 interface
JPEG codec unit
Audio functions Serial sound interface x 4 channels
Renesas SPDIF interface
Timer functions Multifunction 16-bit timer (MTU3) x 8 channels, 32-bit timer x 1 channel
32-bit OS timer x 3 channels
Motor control PWM timer x 8 channels
Watchdog timer
Real-time clock
Connectivity functions USB 2.0 host/function module x 2 channels (host or function selectable)
SD/MMC host interface x 2 channels (must obtain SD card license)
NAND flash interface
Ethernet controller (10 Mbps/100Mbps transfer, IEEE802.3 PHY interface MII and RMII)
SPI multi I/O bus controller x 1 channel (Up to two serial flash memories with multiple I/O bus sizes (single/quad) can be connected to 1 channel/Connectable with one HyperFlash memory, direct execution from CPU supported)
HyperBus controller
Octa memory controller
Serial communication interface with 16-stage FIFO (SCIF) x 5 channels (asynchronous and clock synchronous serial communication possible)
Serial communication interface x 2 channels (smart card interface, IrDA 1.0)
Renesas serial peripheral interface x 3 channels
I2C bus interface x 4 channels
Controller area network (CAN) x 2 channels (CAN-FD supported)
System analog functions Clock pulse generator (CPG): Built-in PLL, maximum 32 times multiplication, built-in SSCG circuit
Direct memory access controller x 16 channels
Interrupt controller (with Arm® PrimeCell® Generic Interrupt Controller [GIC-400])
A/D converter (12-bit resolution) x 8 channels
Debugging interface
CoreSight architecture
JTAG standard pin layout
Optional function Dynamically Reconfigurable Processor (DRP)
Secure features (requires nondisclosure agreement)
Boot modes Boot mode 0: Booting from memory (bus width: 16 bits) connected to the CS0 space
Boot mode 1: Booting from a NAND flash memory with SD controller
Boot mode 2: Booting from a NAND flash memory with MMC controller
Boot mode 3: Booting from a serial NOR flash memory (3.3V) connected to the SPI multi I/O bus space
Boot mode 4: Booting from a OctaFlash connected to the SPI multi I/O bus space
Boot mode 5: Booting from a HyperFlash connected to the SPI multi I/O bus space
Boot mode 6: Booting from a OctaFlash connected to the OctaFlash space
Boot mode 7: Booting from a HyperFlash connected to the HyperFlash space
Power-down modes Sleep mode
Software standby mode
Deep standby mode
Module standby mode

Pin Count/Memory Size Lineup:

SRAM

4096KB
Pins
Package
176
LFBGA
256
LFBGA
272
LFBGA
324
FBGA

Block Diagram:

Block Diagram

*Arm, Cortex, CoreLink, and CoreSight are registered trademarks or trademarks of Arm Limited.

CAN (Controller Area Network): An automotive network specification developed by Robert Bosch GmbH of Germany.

All other names of products or services mentioned here are trademarks or registered trademarks of their respective owners.


DRP Technology and Applications

DRP technology from Renesas is special purpose hardware built into selected RZ Series MPUs that dramatically accelerates image processing algorithms by as much as 10X, or more. It combines the high performance of hardware solutions with the flexibility and expansion capability of a CPU.

Learn More About DRP Technology

DRP Library for RZ/A2M MPUs

1:51
The DRP coprocessor accelerates 2D barcode detection, extraction, data matrix interpolation, and URL decoding in a live video stream.
2:17
The DRP coprocessor accelerates iris detection and extraction for faster, more reliable authentication, enabled by pre-verified DRP libraries.
2:05
The DRP coprocessor accelerates Canny edge detection by more than 10 times compared to CPU-only processing in the RZ/A2M MPU.
1:51
The DRP coprocessor accelerates 2D barcode detection, extraction, data matrix interpolation, and URL decoding in a live video stream.
2:17
The DRP coprocessor accelerates iris detection and extraction for faster, more reliable authentication, enabled by pre-verified DRP libraries.
2:05
The DRP coprocessor accelerates Canny edge detection by more than 10 times compared to CPU-only processing in the RZ/A2M MPU.
1:51
The DRP coprocessor accelerates 2D barcode detection, extraction, data matrix interpolation, and URL decoding in a live video stream.
2:17
The DRP coprocessor accelerates iris detection and extraction for faster, more reliable authentication, enabled by pre-verified DRP libraries.
2:05
The DRP coprocessor accelerates Canny edge detection by more than 10 times compared to CPU-only processing in the RZ/A2M MPU.

Related Videos

4:41
Renesas RZ/A2M microprocessors offer an innovative architecture based on the ARM Cortex®-A9 processor and industry-leading 4MB of on-chip memory.
4:27
The DRP has dynamically reconfigurable processor cores that are programmable in C language and are directly connected to the external I/O ports.
4:41
Renesas RZ/A2M microprocessors offer an innovative architecture based on the ARM Cortex®-A9 processor and industry-leading 4MB of on-chip memory.
4:27
The DRP has dynamically reconfigurable processor cores that are programmable in C language and are directly connected to the external I/O ports.
4:41
Renesas RZ/A2M microprocessors offer an innovative architecture based on the ARM Cortex®-A9 processor and industry-leading 4MB of on-chip memory.
4:27
The DRP has dynamically reconfigurable processor cores that are programmable in C language and are directly connected to the external I/O ports.

You can find an explanation of orderable part numbers here.

 

Resources for Software and Hardware

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e-learning Information for studying and learning about microcontrollers and microprocessors.
FAQ Frequently asked questions and useful hints for development.
Forum A forum and community site to share technical information, questions and opinions with others who use Renesas products.

 

Resources for Software and Hardware

Title Description
e2 studio Renesas eclipse embedded studio, known as e² studio, is a complete development and debug environment based on the popular Eclipse CDT project.

Resources for Software

Title Description
Register definition To be able to use as specified variables, this iodefine.h is defined the peripheral I/O registers.

 

Hardware Design Support

Title Description
IBIS/BSDL IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board. BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing.
Oscillation circuit characteristics Please search for your resonator on its manufacturer's site linked below. If you require optimal oscillation circuit constants for your particular system, please ask the manufacturer of the oscillator.

For main clock resonators:
KYOCERA: Click for oscillation evaluation result.
Circuit CAD data, board CAD data Circuit diagram CAD data and substrate CAD data are offered. Please use it by all means.
You can filter the sample codes and application notes that are displayed using the below filters.

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