The 8V19N490 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. The device supports JESD204B subclass 0 and 1 clocks.
A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency.
The device supports the clock generation of high-frequency clocks from the selected VCO and low-frequency synchronization signals (SYSREF). SYSREF signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The four redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The device is configured through a 3-wire SPI interface and reports lock and signal loss status in internal registers and via a lock detect (LOCK) output. Internal status bit changes can also be reported via the nINT output. The 8V19N490 is ideal for driving converter circuits in wireless infrastructure, radar/imaging, and instrumentation/medical applications.
For information regarding evaluation boards and material, please contact your local sales representative.
[製品選択]テーブル内の製品名をクリックするとSamacSysが提供する回路図シンボル、PCBフットプリント、3D CADモデルがご確認いただけます。 お探しのシンボルやモデルが見つからない場合、Webサイトから直接リクエストできます。
5Gミリ波用ビームフォーミングICのポートフォリオを拡充し、業界最高レベルの送信出力を実現するトランスミッタ/レシーバ「F5288」、「F5268」を発売 | ニュース | 2021年11月10日 | |
Benefits of a Point-of-Use Clock for Jitter Optimization | ブログ | 2021年4月27日 | |
A Reference Design Saved My Bacon | ブログ | 2018年4月27日 | |
CaviumとIDT、タイミングソリューションを共同開発 | ニュース | 2017年12月22日 | |
IDT社、無線基地局RFカード向けに低ノイズのタイミング・チップセットを発表、 業界をリードするタイミング・ポートフォリオを拡大 | ニュース | 2013年6月25日 |