特長
- 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation
- Inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS
- Outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output
説明
Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, and 667MHz.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Temp. Grade | Pb (Lead) Free | Carrier Type |
|---|---|---|---|---|---|---|---|---|
| SSTUAF32868BHLF | Obsolete | N/A | Out of Stock | CABGA | 176# | C | Yes | Tray |
| SSTUAF32868BHLFT | Obsolete | N/A | Out of Stock | CABGA | 176# | C | Yes | Reel |
