特長
- Packaged in 8-pin (150 mil wide) SOIC
- Clock or crystal input
- Low phase noise
- Low jitter
- Exact (0 ppm) multiplication ratios
- Independent output voltage
- Support for 256 times sampling rate
MK2705 - Block Diagram
説明
The MK2705 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source with a 27 MHz crystal. The device uses the latest PLL technology to provide good phase noise and long term jitter characteristics in a small 8-pin package. Contact IDT if you have a requirement for an input and output frequency not included in this document.
