特長
- Output clock frequency from 125MHz to 190MHz (Consult factory for frequency availability)
- Two identical LVPECL output pairs
- Integrated SAW (surface acoustic wave) delay line
- Low jitter 0.5ps rms (over 12kHz-20MHz)
- Ideal for Gigabit Ethernet clock reference
- Output-to-output skew < 100ps
- External XTAL or LVCMOS reference input
- Selectable external feed-through clock input
- STOP clock control (Logic 1 stops output clocks)
- Industrial temperature grade available
- Single 3.3V power supply
- Small 9 x 9 mm SMT (surface mount) package
m902-01 - Block Diagram
説明
The M902-01 is a PLL (Phase Locked Loop) based clock generator that uses an internal VCSO (Voltage Controlled SAW Oscillator) to produce a very low jitter output clock. It is ideal for Gigabit Ethernet. The output clock (frequency of 156.25 or 187.50MHz for example) is provided from two LVPECL clock output pairs. (Specify frequency at time of order.) The accuracy of the output frequency is assured by the internal PLL, which phase-locks the internal VCSO to the reference input frequency (25 or 30MHz for example). The input reference can either be an external crystal, utilizing the internal crystal oscillator, or a stable external clock source such as a packaged crystal oscillator.
