特長
- Integrated Surface Acoustic Wave (SAW) delay line
- Low phase jitter of < 0.5ps RMS, typical (12kHz to 20MHz or 50kHz to 80MHz)
- Output frequencies of 15MHz to 700MHz
- LVPECL clock output (CML and LVDS options available)
- Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
- Loss of Lock (LOL) output pin
- Narrow bandwidth control input (NBW pin)
- Hitless Switching (HS) options with or without Phase Build-out (PBO) are available for SONET (GR-253)/SDH (G.813) MTIE and TDEV compliance during reference clock reselection
- Industrial temperature grade available
- Single 3.3V power supply
- Small 9mm x 9mm surface mount package
m2020 - Block Diagram
説明
The M2020/21 is a Voltage Controlled SAW Oscillator (VCSO) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting 2.5GB to 10GB data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M2020/21 module includes a proprietary Surface Acoustic Wave (SAW) delay line as part of the VCSO. This results in a high-frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter.
