特長
- Ideal for OC-48/192 data clock
- Integrated surface acoustic wave (SAW) delay line
- VCSO frequency from 300MHz to 700MHz (Specify VCSO center frequency at time of order)
- Low phase jitter of < 0.5ps RMS, typical (12kHz to 20MHz or 50kHz to 80MHz)
- Pin-selectable configuration
- Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
- Industrial temperature available
- Single 3.3V power supply
- Small 9mm x 9mm surface mount package
m2004-02 - Block Diagram
説明
The M2004-02 is a Voltage Controlled SAW Oscillator (VCSO) based clock generator PLL designed for clock frequency translation and jitter attenuation in a high-speed data communications system. The clock multiplication ratio and output divider ratio are pin selectable. External loop components allow the tailoring of PLL loop response.
