Name: 9ZXL1951D - 19-Output DB1900ZL PCIe Zero-Delay/Fanout Clock Buffer
Brand: Renesas Electronics Corporation
SKU: 9ZXL1951D - 19-Output DB1900ZL PCIe Zero-Delay/Fanout Clock Buffer
Price: 3.59613 USD
Availability: InStock

特長

LP-HCSL outputs with 85Ω Zout; eliminates 76 termination resistors, saves 130mm² area
PCIe Gen 1–5 compliance
8 OE# pins configurable to control up to 16 outputs; easy power management
9 selectable SMBus addresses; multiple devices can share same SMBus segment
Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
Spread spectrum compatible; tracks spreading input clock for EMI reduction
100MHz PLL mode; UPI support
DIF input and DIF outputs on outer row of pins; easy board routing
6 x 6 mm dual-row 80-GQFN; smallest 19-output Z-buffer

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説明

The 9ZXL1951D is a second-generation, enhanced performance DB1900ZL derivative buffer. The part is a pin-compatible upgrade to the 9ZXL1951A, offering a much improved phase jitter performance. It has 8 OE# pins that can be configured via SMBus to control up to 16 of the device's 19 outputs, and is packaged in a 6 x 6 mm QFN package for maximum space savings. A fixed external feedback maintains low drift for critical QPI/UPI applications.

パラメータ

属性	値
Diff. Outputs	19
Diff. Output Signaling	LP-HCSL
Output Freq Range (MHz)	1 - 400
Diff. Inputs	1
Diff. Input Signaling	HCSL
Accepts Spread Spec Input	Yes
Power Consumption Typ (mW)	712
Supply Voltage (V)	3.3 - 3.3
Output Type	LP-HCSL
Diff. Termination Resistors	0
Package Area (mm²)	100
Battery Backup	No
Battery Seal	No
CPU Supervisory Function POR	No
Crystal Frequency Trimming	No
Frequency Out Pin	No
Inputs (#)	1
Input Freq (MHz)	33 - 150
Function	Zero Delay Buffer
Input Type	HCSL
Output Banks (#)	1
Core Voltage (V)	3.3
Output Voltage (V)	0.7

パッケージオプション

Pkg. Type	Pkg. Dimensions (mm)	Lead Count (#)	Pitch (mm)
VFQFPN	6.0 x 6.0 x 0.85	80	0.5

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

The 9ZXL1951D is designed to create clocks for PCI Express Generation 4. This video demonstrates how the reference clock for the 9ZXL1951D does not need to be PCI Express Gen4 compliant. When using the Low Bandwidth mode, the 9ZXL1951D will attenuate jitter so its output clocks still pass PCI Express Gen4, even when the input clock only passes PCI Express Gen3. This is most useful when the clock has spread spectrum modulation because it is very difficult to make a very low noise spreading clock.

Related Resources

A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.

Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.

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9ZXL1951D

19-Output DB1900ZL PCIe Zero-Delay/Fanout Clock Buffer

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