特長
- High-voltage types (20V rating)
- Medium-speed operation
- Fully static operation
- Buffered inputs and outputs
- 100% tested for quiescent current at 20V
- Standardized symmetrical output characteristics
- Common reset
- 5V, 10V and 15V parametric ratings
- Maximum input current of 1µa at 18V over full package temperature range:
- 100nA at 18V and 25 °C
- Noise margin (over full package temperature range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
- Meets all requirements of JEDEC tentative standard No. 13B, "Standard Specifications For Description Of "B" Series CMOS devices
CD4024BMS Functional Diagram
説明
The CD4020BMS (14-stage), CD4024BMS (7-stage), and CD4040BMS (12-stage) are ripple carry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered. The CD4020BMS, CD4024BMS and CD4040BMS are supplied in these 14-lead outline packages: Braze Seal DIP H4W, H4Q and H4X; Frit Seal DIP H1F and H1B; and Ceramic Flatpack H6W and H3W.
アプリケーション
- Control counters
- Timers
- Frequency dividers
- Time-delay circuits
