特長
- 12-bit pipelined ADC core
- Clock input divider by 2 for less jitter contribution
- CMOS or LVDS DDR digital outputs
- Duty cycle stabilizer
- Fast Out of Range (OTR) detection
- Flexible input voltage range: 1 V p-p to 2 V p-p
- HVQFN40 package
- INL ±
- 0.25 LSB, DNL ±
- 0.12 LSB
- Input bandwidth, 600 MHz
- Offset binary, 2's complement, gray code
- Pin compatible with the ADC1410S series and the ADC1010S series
- Power-down and Sleep modes
- Sample rate up to 65 Msps
- Serial Peripheral Interface (SPI)
- Single 3 V supply
- SNR, 70.5 dBFS
- SFDR, 90 dBc
ADC1210S065HN - Block Diagram
説明
The ADC1210S is a single-channel 12-bit Analog-to-Digital Converter optimized for high dynamic performances and low power consumption. Pipelined architecture and output error correction ensure the ADC1210S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, by a separate digital output supply. It supports the LVDS DDR output standard. An integrated SPI allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more.
