特長
- 19 HCSL output pairs
- Fixed feedback path
- Phase jitter: PCIe Gen 4 < 0.5ps rms
- Phase jitter: UPI 9.6GT/s < 0.1ps rms
- PLL or bypass mode; PLL can de-jitter incoming clock
- 9 selectable SMBus Addresses
- 8 dedicated OE# pins
- 100MHz or 133MHz PLL mode; legacy QPI support
- Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
- Spread spectrum compatible
- SMBus interface
- 10mm × 10mm 72-QFN package
9ZX21901D - Block Diagram
説明
The 9ZX21901D is a second-generation DB1900Z differential buffer for Intel Purley and newer platforms. The part is backward compatible with the 9ZX21901C while offering much-improved phase jitter performance. Fixed external feedback maintains low drift for critical QPI/UPI applications. In bypass mode, the 9ZX21901D can provide outputs up to 400MHz.
パラメータ
| 属性 | 値 |
|---|---|
| Diff. Outputs | 19 |
| Diff. Output Signaling | HCSL |
| Output Freq Range (MHz) | 33 - 400 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 1676 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | LP-HCSL |
| Diff. Termination Resistors | 0 |
| Package Area (mm²) | 100 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 33 - 150 |
| Function | Zero Delay Buffer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 0.7 |
| Product Category | PCI Express Clocks, Processor Clock Buffers, Zero Delay Buffers |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 10.0 x 10.0 x 1.0 | 72 | 0.5 |
