特長
- Features/Benefits:
- Supports programmable spread percentage and frequency
- Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning
- Low power differential clock outputs (No 50Ω resistor to GND needed)
- Programmable output skew
- Programmable watchdog safe frequency
- Integrated 33ohm series resistor on all differential outputs
- Low power supply voltage support for differential outputs
- Meets PCIEX Gen2 specifications
- Uses 1.5V core voltage for ultra low power design
- Output programmable slew rate controls
- Key Specifications:
- CPU output cycle-cycle jitter < 85ps
- PCIEX output cycle-cycle jitter < 125ps
- +/- 100ppm frequency accuracy for all output clocks
- CPU-AGP skew ~ 1.1ns typical
- AGP-PCIA skew ~ 1.06ns typical
- AGP-PCIB skew ~ 1.46ns typical
- CPU1-PCIA skew ~ 2.16ns typical
- CPU1-PCIB skew ~ 2.46ns typical
説明
Ultra low power main clock for VIA VX900 chipset