パッケージ情報
| Pkg. Type: | TSSOP |
| Pkg. Code: | PAG56 |
| Lead Count (#): | 56 |
| Pkg. Dimensions (mm): | 14.0 x 6.1 x 1.0 |
| Pitch (mm): | 0.5 |
環境及び輸出分類情報
| Pb (Lead) Free | Yes |
| Moisture Sensitivity Level (MSL) | 1 |
| ECCN (US) | |
| HTS (US) |
製品スペック
| Pkg. Type | TSSOP |
| Lead Count (#) | 56 |
| Pb (Lead) Free | Yes |
| Carrier Type | Reel |
| 100M Non-SSC Outputs | 1 |
| 100M SSC Outputs | 7 |
| 25M Outputs | 1 |
| Advanced Features | CPU 100M-400M output pair(s), SRC/DOT96 output pair(s), SRC/SE output pair(s), 14.318M output(s), 48M output(s) |
| App Jitter Compliance | PCIe Gen1 |
| C-C Jitter Max P-P (ps) | 85 |
| Chipset Manufacturer | Intel |
| Clock Spec. | CK505 |
| Core Voltage (V) | 3.3 |
| Die Form | No |
| Diff. Output Signaling | HCSL |
| Diff. Termination Resistors | 22 |
| Freq. Accuracy Init. (± PPM) | 100 |
| Function | Clock Generator |
| Input Freq (MHz) | 14.32 - 14.32 |
| Length (mm) | 14 |
| MOQ | 2000 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Freq Range (MHz) | 14.32 - 400 |
| Output Skew (ps) | 100 |
| Output Voltage (V) | 3.3V, 0.7V |
| Outputs (#) | 19 |
| PCI 33.33M Outputs (#) | 5 |
| PCIe Generation | Gen1 |
| Package Area (mm²) | 85.4 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 14.0 x 6.1 x 1.0 |
| Power Consumption Typ (mW) | 450 |
| Qty. per Carrier (#) | 0 |
| Qty. per Reel (#) | 2000 |
| Reel Size (in) | 13 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 1.05 - 3.3 |
| Tape & Reel | Yes |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 1 |
| Width (mm) | 6.1 |
| Xtal Freq (MHz) | 14.32 - 14.32 |
| Xtal Inputs (#) | 1 |
| 掲載 | No |
9LP505-2 に関するリソース
説明
CK505 clock, 56-pin Intel Yellow Cover part