パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NDG48 |
| Lead Count (#): | 48 |
| Pkg. Dimensions (mm): | 6.0 x 6.0 x 0.9 |
| Pitch (mm): | 0.4 |
環境及び輸出分類情報
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
製品スペック
| Lead Count (#) | 48 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 490 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Assembly Location | THAILAND |
| Wafer Fab Location | TAIWAN |
| Accepts Spread Spec Input | Yes |
| Additive Phase Jitter Typ RMS (fs) | 100 |
| Additive Phase Jitter Typ RMS (ps) | 0.1 |
| Advanced Features | Power Down Tolerant, Flexible Power Sequencing, Multiple SMBus addresses |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5 |
| Architecture | Common, SRNS, SRIS |
| C-C Jitter Max P-P (ps) | 125 |
| Core Voltage (V) | 3.3V |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 2 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 8 |
| Diff. Termination Resistors | 0 |
| Feedback Input | No |
| Function | Multiplexer |
| Input Freq (MHz) | 1 - 400 |
| Input Type | HCSL |
| Inputs (#) | 2 |
| Length (mm) | 6 |
| MOQ | 490 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 1 - 400 |
| Output Impedance | 85 |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL |
| Output Voltage (V) | 0.4V |
| Outputs (#) | 8 |
| PLL | No |
| Package Area (mm²) | 16 |
| Pitch (mm) | 0.4 |
| Pkg. Dimensions (mm) | 6.0 x 6.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 178 |
| Product Category | Clock Multiplexers, PCI Express Clocks |
| Prog. Clock | No |
| Reference Output | No |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 0.9 |
| Width (mm) | 6 |
9DML2855 に関するリソース
説明
The 9DML2855 is a 2-input, 8-output clock multiplexer supporting PCIe Gen1–5 and DB2000Q applications. The device supports complex clock architecture like CC, SRIS, and SRNS while providing very low additive jitter. Flexible Power Sequencing (FPS) ensures well-defined behavior under various power-up scenarios, while Power Down Tolerant (PDT) ESD protection on all input pins allows input pins to be driven before VDD is applied. The 9DML2855 also features an OE# pin for each output and supports PCIe CLKREQ# functionality.
For information regarding evaluation boards and material, please contact your local sales representative.