特長
- 2 - Differential CPU Clock Pairs @ 3.3V
- 8 - PCI (3.3V) @ 33.3MHz including 2 1x/2x selectable PCI clocks
- 3 - PCI_F/PCI selectable (3.3V) @ 33.3MHz
- 1 - USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
- 1 - REF (3.3V) @ 14.318MHz
- 4 - 3V66 (3.3V) @ 66.6MHz
- 1 - VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
- Selectable 1X or 2X strength for REF and PCI via SMBus interface
- Programmable group to group skew
- Linear programmable frequency and spreading %
- Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#.
- Uses external 14.318MHz crystal
- Stop clocks and functional control available through SMBus interface.
- CPU Output Jitter <150ps
- 3V66 Output Jitter <250ps
- CPU Output Skew <100ps
950818 - Block Diagram
説明
Frequency Generator with 200MHz Differential CPU Clocks
