概要
説明
The IDT9112-16 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz.
特長
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Zero input - output delay
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Frequency range 25 - 133 MHz (3.3V)
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High loop filter bandwidth ideal for Spread Spectrum applications
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Less than 200 ps Jitter between outputs
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Skew controlled outputs
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Skew less than 250 ps between outputs
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Available in 8 pin 150 mil SOIC or 173 mil TSSOP package.
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3.3V ±10% operation
製品比較
アプリケーション
設計・開発
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