特長
- Clock signal division and distribution
- SiGe technology for high-frequency and fast signal rise/fall times
- Four low-skew LVPECL clock outputs
- Supports frequency division of ÷1, ÷2, ÷4 and ÷8
- Maximum frequency: 2.5GHz
- Maximum output skew: 50ps (maximum)
- Maximum LVPECL output rise/fall time: 200ps (maximum)
- 3.3V or 2.5V core and output supply mode
- Supports 1.8V I/O logic levels for all control pins
- -40 °C to 85 °C ambient operating temperature
- Available in lead-free (RoHS 6) package
説明
The 8V79S674 is a clock divider and fanout buffer designed for clock signal division in wireless base station radio equipment boards. The device is optimized to deliver excellent additive phase jitter performance. The 8V79S674 uses SiGe technology for an optimum of high clock frequency and low phase noise performance, combined with high power supply noise rejection. It offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four low-skew LVPECL outputs are available and support clock output frequencies up to 2.5GHz (÷1 frequency division). Outputs can be disabled to save power consumption if not used. The device is packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication, and networking end equipment requirements.
アプリケーション
- Clock signal division in wireless base station radio equipment boards
