特長
- Ten low skew, low additive jitter LVPECL outputs
- Two selectable, differential LVPECL clock inputs
- Differential pairs can accept the following differential input levels: LVDS and LVPECL
- Maximum input clock frequency: 2.5GHz
- LVCMOS interface levels for the control input (input select)
- Output skew: 15ps (typical)
- Propagation delay: 250ps (typical)
- Additive phase jitter, RMS
- fREF = 155.52MHz (12kHz - 20MHz): 77fs (typical)
- Full 3.3V and 2.5V supply voltage
- Maximum device current consumption (IEE): 100mA (typical)
- Lead-free (RoHS 6) 32-Lead VFQFN package
- -40°C to 85°C ambient operating temperature
8T53S111I - Block Diagram
説明
The 8T53S111I is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8T53S111I is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8T53S111I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and ten low skew outputs are available. The integrated VREF voltage generator enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
