特長
- Two 1:6, low skew, low additive jitter LVPECL fanout buffers
- Two differential clock inputs
- Differential pairs can accept the following differential input levels: LVDS and LVPECL
- Maximum input clock frequency: 2GHz
- Output bank skew: 12ps (typical)
- Propagation delay: 280ps (typical)
- Low additive phase jitter, RMS: fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: 49fs (typical)
- Full 3.3V and 2.5V supply voltage modes
- Maximum device current consumption (IEE): 100mA (typical)
- Available in Lead-free (RoHS 6), 40-Lead VFQFN package
- -40°C to 85°C ambient operating temperature
- Supports case temperature ≤105°C operations
8SLVP2106I - Block Diagram
説明
The 8SLVP2106I is a high-performance differential dual 1:6 LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP2106I is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP2106I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two independent buffers with six low skew outputs each are available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
パラメータ
| 属性 | 値 |
|---|---|
| Temp. Range (°C) | -40 to 85°C (Tc ≤ 105°C) |
| Product Category | Clock Buffers & Drivers, RF Buffers |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 6.0 x 6.0 x 0.9 | 40 | 0.5 |
