特長
- Fully integrated PLL
- Fourteen LVCMOS/LVTTL outputs
- twelve clock outputs, one feedback, one sync
- Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs
- CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL
- CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- Output frequency range: 8.33MHz to 125MHz
- VCO range: 200MHz to 480MHz
- Output skew: 550ps (maximum)
- Cycle-to-cycle jitter: ±100ps (typical)
- Full 3.3V supply voltage
- -40°C to 85°C ambient operating temperature
- Available in lead-free RoHS compliant package
- Compatible with PowerPC™ and Pentium™ Microprocessors
説明
The 87973I is a LVCMOS/LVTTL clock generator from IDT. The 87973I has three selectable inputs and provides fourteen LVCMOS/LVTTL outputs. The 87973I is a highly flexible device. The three selectable inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 8.33MHz to125MHz. The input frequency range is 5MHz to 120MHz. The 87973I also has a QSYNC output which can by used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another.
