特長
- Fully integrated PLL
- Fourteen LVCMOS/LVTTL outputs
- (12) clocks, (1) feedback, (1) sync
- Selectable crystal oscillator interface or LVCMOS/LVTTL reference clock inputs
- CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL
- Output frequency range: 8.33MHz to 125MHz
- VCO range: 200MHz to 480MHz
- Output skew: 550ps (maximum)
- Cycle-to-cycle jitter: ±100ps (typical)
- Full 3.3V supply voltage
- -40°C to 85°C ambient operating temperature
- Available in lead-free RoHS-compliant package
- Compatible with PowerPC™ and Pentium™ Microprocessors
説明
The 87972I is a low skew, LVCMOS/LVTTL Clock Generator. The 87972I has three selectable inputs and provides fourteen LVCMOS/LVTTL outputs. The 87972I is a highly flexible device. Using the crystal oscillator input, it can be used to generate clocks for a system. All of these clocks can be the same frequency or the device can be configured to generate up to three different frequencies among the three output banks. Using one of the single ended inputs, the 87972I can be used as a zero delay buffer/multiplier/divider in clock distribution applications. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 8.33MHz to125MHz. Input frequency range is 5MHz to 120MHz. The 87972I also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period of the faster clock prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another.
