パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | SOIC |
| Pkg. Code: | PSG20 |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 12.8 x 7.6 x 2.34 |
| Pitch (mm): | 1.27 |
環境及び輸出分類情報
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
製品スペック
| Lead Count (#) | 20 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 37 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | 0 to 70°C |
| Advanced Features | Feedback Input |
| C-C Jitter Max P-P (ps) | 30 |
| Core Voltage (V) | 3.3 |
| Feedback Input | Yes |
| Input Freq (MHz) | 31.25 - 700 |
| Input Type | HCSL, HSTL, LVDS, LVPECL, SSTL |
| Inputs (#) | 1 |
| Length (mm) | 12.8 |
| MOQ | 37 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 31.25 - 700 |
| Output Skew (ps) | 35 |
| Output Type | LVDS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 1 |
| Package Area (mm²) | 97.3 |
| Phase Jitter Max RMS (ps) | 52 |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 12.8 x 7.6 x 2.34 |
| Pkg. Type | SOIC |
| Prog. Clock | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Thickness (mm) | 2.34 |
| Width (mm) | 7.6 |
| 掲載 | No |
8745B-21 に関するリソース
説明
The 8745B-21 is a highly versatile 1:1 LVDS Clock Generator. The 8745B-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clock. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.