特長
- Five differential 3.3V LVPECL output pairs
- Selectable differential input pairs
- CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL
- Output frequency range: 31.25MHz to 700MHz
- Input frequency range: 31.25MHz to 700MHz
- VCO range: 250MHz to 700MHz
- External feedback for “zero delay” clock regeneration with configurable frequencies
- Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
- Static phase offset: 200ps (maximum)
- Cycle-to-Cycle jitter: 50ps (maximum)
- Output skew: 55ps (maximum)
- 3.3V output operating supply
- -40 °C to 85 °C ambient operating temperature
- Lead-free (RoHS 6) packaging
8735Bi-01 - Block Diagram
説明
The 8735BI-01 is a highly versatile 1:5 differential- to-3.3V LVPECL clock generator. The 8735BI-01 has a fully integrated PLL and can be configured as zero delay buffer, multiplier, or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider, and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, and 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
