特長
- Three differential HSTL output pairs
- Selectable differential CLKx, nCLKx input pairs
- CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL
- Output frequency range: 350MHz to 950MHz
- Input frequency range: 350MHz to 950MHz
- VCO range: 970MHz to 2250MHz
- External feedback for "zero delay" clock regeneration with configurable frequencies
- Static phase offset: ±100ps (maximum)
- Cycle-to-cycle jitter: 25ps (maximum)
- Output skew: 20ps (maximum)
- 3.3V operating voltage supply
- Selectable DDR3 or DDR3 low voltage output
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
説明
The 872S480 is a Zero Delay Clock Generator with hitless input clock switching capability. The 872S480 is ideal for use in redundant, fault tolerant clock trees where low jitter frequency synthesis are critical. The device receives two differential clock signals from which it generates two outputs with "zero" delay. The output and feedback dividers are configured to allow for a 1:1 frequency generation ratio. The 872S480 Dynamic Clock Switch (DCS) circuit continuously monitors both input clock signals. Upon detection of an invalid clock input (stuck LOW or HIGH for at least one complete clock period of the VCO feedback frequency), the loss of reference monitor will be set HIGH. If that clock is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. Once the primary clock is restored to a good state, the DCS will automatically switch back to the primary clock input. The low jitter characteristics with input clock monitoring and DCS capability make the 872S480 an ideal choice for DDR3 applications requiring fault tolerant reference clocks.
