特長
- Two 0.7V HCSL differential output pairs
- One differential clock input
- CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
- Input frequency range: 98MHz to 128MHz
- Output frequency range: 98MHz to 640MHz
- VCO range: 490MHz - 640MHz
- Cycle-to-cycle jitter: 45ps (maximum)
- Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs
- Full 3.3V supply mode
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
説明
The 871002I-02 is a high performance Jitter Attenuator designed for use in PCI Express®™ systems. In some PCI Express® systems, such as those found in desktop PCs, the PCI Express® clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 871002I-02 has two PLL bandwidth modes: 350kHz and 2200kHz. The 350kHz mode provides the maximum jitter attenuation, but it also results in higher PLL tracking time. In this mode, the spread spectrum modulation may also be attenuated. The 2200kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. The 871002I-02 can be set for different modes using the F_SELx pins as shown in Table 3C. The 871002I-02 uses IDT 3rd Generation FemtoClockTM PLL technology to achieve the lowest possible phase noise. The device is packaged in a small 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express® add-in cards.