特長
- Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
- Single LVCMOS/LVTTL clock input
- CLK accepts the following input levels: LVCMOS or LVTTL
- Output frequency range: 62.5MHz to 250MHz
- Input frequency range: 62.5MHz to 250MHz
- External feedback for "zero delay" clock regeneration with configurable frequencies
- Fully integrated PLL
- Cycle-to-cycle jitter, (F_SEL = 1): 45ps (maximum)
- Output skew: 60ps (maximum)
- Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V - 5V tolerant input
- -40°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
説明
The 86004-01 is a high performance 1-to-4 LVCMOS/LVTTL Clock Buffer and a member of the family of High Performance Clock Solutions from IDT. The 86004-01 has a fully integrated PLL and can be configured as zero delay buffer and has an input and output frequency range of 62.5MHz to 250MHz. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output divider.