特長
- High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer
- One differential 3.3V LVPECL output
- Four selectable CLK, nCLK inputs
- CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
- Maximum output frequency: 750MHz
- Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx input
- Part-to-part skew: 415ps (maximum)
- Propagation delay: 1.5ns (maximum)
- LVPECL mode operating voltage supply range: VCC = 3.135V to 3.465V, VEE = 0V
- ECL mode operating voltage supply range: VCC = 0V, VEE = -3.135V to -3.465V
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
説明
The 85357I-01 is a 4:1 or 2:1 Differential-to-3.3V LVPECL / ECL clock multiplexer which can operate up to 750MHz. The 85357I-01 has 4 selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The device can operate using a 3.3V LVPECL (VEE = 0V, VCC = 3.135V to 3.465V) or 3.3V ECL (VCC = 0V, VEE = -3.135V to -3.465V). The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. Leaving one input unconnected (pulled to logic low by the internal resistor) will transform the device into a 2:1 multiplexer. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects CLK0, nCLK0).
