特長
- Four differential output HSTL compatible outputs
- Selectable differential CLK, nCLK or LVPECL clock inputs
- CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
- PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL
- Maximum output frequency: 650MHz
- Translates any single-ended input signal to HSTL levels with resistor bias on nCLK input
- Additive phase jitter, RMS: 0.082ps (typical), 100MHz fOUT
- Additive phase jitter, RMS: 0.190ps (typical), 120MHz fOUT
- Output skew: 30ps (maximum)
- Part-to-part skew: 200ps (maximum)
- 3.3V core, 1.8V output operating supply
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) packages
8523 - Block Diagram
説明
The 8523 is a low skew, high performance 1-to-4 Differential-to-HSTL Fanout Buffer. The 8523 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8523 ideal for those applications demanding well defined performance and repeatability.
