特長
- Clock generation of: 50MHz, 62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz and 312.5MHz
- Two differential CML clock output pairs
- Crystal interface designed for 25MHz, 18pF parallel resonant crystal
- RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 400fs (typical), 3.3V
Offset Noise Power
100Hz................... -102.4 dBc/Hz
1kHz................... -119.4 dBc/Hz
10kHz................... -124.8 dBc/Hz
100kHz................... -125.7 dBc/Hz - LVCMOS interface levels for the control inputs
- Full 3.3V and 2.5V supply voltage
- Available in lead-free (RoHS 6) 32 VFQFN package
- -40°C to 85°C ambient operating temperature
845252I - Block Diagram
説明
The 845252I is a 3.3V/2.5V CML clock generator designed for Ethernet applications. The device synthesizes either a 50MHz, 62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz or 312.5MHz clock signal with excellent phase jitter performance. The clock signal is distributed to two low-skew differential CML outputs. The device is suitable for driving the reference clocks of Ethernet PHYs. The device supports 3.3V and 2.5V voltage supply and is packaged in a small, lead-free (RoHS 6) 32-lead VFQFN package. The extended temperature range supports telecommunication, wireless infrastructure and networking end equipment requirements.
