特長
- Four differential HSTL output pairs
- Crystal oscillator interface: 25MHz
- Output frequency: 100MHz or 200MHz
- RMS phase jitter @ 200MHz (12kHz - 20MHz): 1.229ps (typical)
- Cycle-to-cycle jitter: 25ps (maximum)
- I2C support with readback capabilities up to 400kHz
- Spread Spectrum for electromagnetic interference (EMI) reduction
- 3.3V core/1.5V to 2.0V output operating supply
- 0°C to 70°C ambient operating temperature
- Available lead-free (RoHS 6) package
- PCI Express Gen2 Jitter Compliant
842S104E - Block Diagram
説明
The 842S104E is a PLL-based clock generator specifically designed for PCI Express™ Clock Generation 2 applications. This device generates either a 200MHz or 100MHz differential HSTL clock from an input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference is applied to the XTAL_IN pin with the XTAL_OUT pin left floating.The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -0.5%.The 842S104E is available in a lead-free 24-Lead package.
