特長
- 2:1 differential clock/data multiplexer with fanout
- Two selectable, differential inputs
- Each differential input pair can accept the following levels: HCSL, LVHSTL, LVDS and LVPECL
- One differential HCSL output
- Maximum input/output clock frequency: 700MHz (maximum)
- Maximum input/output data rate: 1400Mb/s (NRZ)LVCMOS interface levels for all control inputs
- Input skew: 55ps (maximum)
- Part-to-part skew: 400ps (maximum)
- Full 3.3V supply voltage
- Available in lead-free (RoHS 6) 16 TSSOP package
- -40°C to 85°C ambient operating temperature
831721I - Block Diagram
説明
The 831721I is a high-performance, differential HCSL clock/data multiplexer and fanout buffer. The device is designed for the multiplexing of high-frequency clock and data signals. The device has two differential, selectable clock/data inputs. The selected input signal is output at one differential HCSL output. Each input pair accepts HCSL, LVDS, and LVPECL levels. The 831721I is characterized to operate from a 3.3V power supply. Guaranteed input, output-to-output and part-to-part skew characteristics make the 831721I ideal for those clock and data distribution applications demanding well-defined performance and repeatability. The 831721I supports the clock multiplexing and distribution of PCI Express Generation 1, 2 and 3 clock signals.
