特長
- Four LVCMOS / LVTTL outputs
- LVCMOS / LVTTL clock input
- CLK can accept the following input levels: LVCMOS, LVTTL
- Maximum output frequency: 200MHz
- Additive phase jitter, RMS: 0.173ps (typical) @ 3.3V
- Output skew: 45ps (maximum) @ 3.3V
- Part-to-part skew: 500ps (maximum)
- Small 8 lead SOIC package saves board space
- 3.3V input, outputs may be either 3.3V or 2.5V supply modes
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) compliant package
説明
The 8304 is a low skew, 1-to-4 Fanout Buffer. The 8304 is characterized at full 3.3V for input (VDD), and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and part-to-part skew characteristics make the 8304 ideal for those clock distribution applications demanding well defined performance and repeatability.