メインコンテンツに移動
ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation)

ルネサスのタイミング製品ポートフォリオは、SiTime社により買収されました。

データシート、各種ドキュメント、およびサンプルのご注文につきましては、2026年末まで引き続きRenesas.comにてご利用いただけます。新規設計、製品のご購入、サポート、および製品に関するお問い合わせにつきましては、SiTime.com をご利用いただくか、[email protected]までメールでお問い合わせください。SiTime社への全面的な移行は、2026年末までに完了する見込みです。

特長

  • Two LVCMOS/LVTTL outputs, 17? impedance Each output supports independent frequency selection at 25MHz, 62.5MHz, 125MHz, and 156.25MHz
  • Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz
  • Attenuates the phase jitter of the input clock by using a low-cost pullable fundamental mode VCXO crystal
  • VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection
  • FemtoClock frequency multiplier provides low jitter, high frequency output
  • Absolute pull range: ±50ppm
  • FemtoClock VCO frequency: 625MHz
  • RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz - 20MHz): 1.1ps (typical)
  • 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

説明

The 810252BI-03 is a member of the family of high performance clock solutions from Renesas. The 810252BI-03 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock® frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-TQFP, E-Pad and 32- VFQFN packages and supports industrial temperature range.

適用されたフィルター